Verilog assign command

I was unhappy the way Verilog’s assign command was described online. Therefore I would like to share my way to explain it. It’s actually damn simple

assign is described as ‘continuous assignment statement’. Therefore, when you assign a register to a wire, it keeps bind forever. Assigning a to b and changing b means changing a. Be aware, that the left term has to be a wire and the right one has to be some sort of value container (eg. reg). So assigning a value to a is not possible.

module assign_test();
  wire [7:0] a;
  reg [15:0] b = 'h3;
 
  // a reads bits 7 to 0 of b
  assign a = b[7:0];
  // modify b 5 time units later
  always b = #5 b + 'hA;
 
  always #10 $display("reg b is %h", b);
  always #10 $display("wire a is %h", a);
  initial #21 $finish();
endmodule

The output is:

reg b is 000d
wire a is 0d
reg b is 0021
wire a is 21

Verilog assign command