Lukas' Weblog

In discrete mathematics, you often define chains of logical operations. XOR has an issue, not everybody is aware of. If it’s used with 3 variables, it loses its most important behaviour: Indicating that only one value is set to True.

In the end, the XOR keeps associative for 3 variables: (A ⊕ B) ⊕ C = A ⊕ (B ⊕ C). For any greater number of variables the behaviour is in no intuitive relation with 2-var-XOR any longer:

If you want to experiment with XOR, I want to refer to my article Truthtable with python and XOR is in python a caret “^”.

Probably such advertisements are not attractive for everybody :-/

I will explain it for Mozilla Thunderbird since this is my current feed reader. Just leave out steps 3, 4, 6 and 7 for any other feed reader.

1. Get the name of the twitter user.
2. Get the ID of the twitter user by name.
3. Open Thunderbird, select the top-level element containing your RSS feeds.
4. Select “Manage subscriptions” and click “Add”.
5. The feed URL is http://twitter.com/statuses/user_timeline/<userID>.rss (with the placeholder replaced)
6. Click “Ok” to subscribe and move the RSS-Feed to any subfolder you would like to place it.
7. Prefer “View” > “Feed Message Body As” > “Plain Text” and “Summary”

Why “non-existent”? Because Twitter has dropped support for user RSS feeds some time ago. The feeds still exist, but should not be used. However I like RSS and was using this feature for the last 2 years continuously. This decision annoys me

I was unhappy the way Verilog’s assign command was described online. Therefore I would like to share my way to explain it. It’s actually damn simple

assign is described as ‘continuous assignment statement’. Therefore, when you assign a register to a wire, it keeps bind forever. Assigning a to b and changing b means changing a. Be aware, that the left term has to be a wire and the right one has to be some sort of value container (eg. reg). So assigning a value to a is not possible.

module assign_test();
  wire [7:0] a;
  reg [15:0] b = 'h3;
 
  // a reads bits 7 to 0 of b
  assign a = b[7:0];
  // modify b 5 time units later
  always b = #5 b + 'hA;
 
  always #10 $display("reg b is %h", b);
  always #10 $display("wire a is %h", a);
  initial #21 $finish();
endmodule

The output is:

reg b is 000d
wire a is 0d
reg b is 0021
wire a is 21

Input:
$a = array();
$b = $a['a'];
var_dump($a);

Output:
array(0) { }

Input:
$a = array();
$b = &$a['a'];
var_dump($a);

Output:
array(1) { ["a"]=> &NULL }

Accessing elements modifies state. I hate this.

I think mathlibplot is responsible